pub async fn handler(input: Input) -> Result<(), Error> {
    let Input { mut i2c1, exti4, gpio_b, gpio_c } = input;
    // APDS-9960 interrupt events stream read from B4 pin.
    let mut exti4_stream = exti4.create_saturating_stream();
    let mut apds9960 = Apds9960Drv::init();
    let mut gestures = Gestures::init(&mut apds9960, &mut i2c1).await?;
    // Wait for a falling edge trigger on PB4.
    while exti4_stream.next().await.is_some() {
        // Repeat until PB4 is back to the high level.
        while !gpio_b.gpio_idr.load().idr4() {
            // Read APDS-9960 FIFO buffer.
            match gestures.advance(&mut apds9960, &mut i2c1).await? {
                // Turn on the LED.
                Some(Gesture::Up) => gpio_c.gpio_bsrr.store(|r| r.set_br13()),
                // Turn off the LED.
                Some(Gesture::Down) => gpio_c.gpio_bsrr.store(|r| r.set_bs13()),
                _ => {}
            }
        }
    }
    Ok(())
}

$ # uncomment `trace_port` option in `src/lib.rs`
$ just flash
$ just heaptrace
^C
$ drone heap generate --pools 8
 Block Size | Max Load | Total Allocations
------------+----------+-------------------
          1 |        7 |                 7
          8 |        3 |               748
         12 |       11 |               756
         28 |        3 |               748
         56 |        1 |                87
         68 |        1 |               220
        128 |        1 |                 1
        152 |        1 |                 1

Maximum heap load: 651 / 1.99%

=============================== OPTIMIZED LAYOUT ===============================
[heap.main]
size = "32K"
pools = [
    { block = "4", capacity = 522 },
    { block = "12", capacity = 515 },
    { block = "28", capacity = 289 },
    { block = "56", capacity = 143 },
    { block = "68", capacity = 90 },
    { block = "152", capacity = 15 },
]
# fragmentation: 36 / 0.11%
# hint: replace the existing [heap] section in Drone.toml

use crate::consts::{FLASH_WS, PLL_M, PLL_N, PLL_P};
use drone_cortexm::reg::prelude::*;
use drone_stm32_map::reg;

fn init_sys_clk(
    mut rcc_cr: reg::rcc::Cr<Urt>,
    mut rcc_pllcfgr: reg::rcc::Pllcfgr<Urt>,
    mut rcc_cfgr: reg::rcc::Cfgr<Urt>,
    mut flash_acr: reg::flash::Acr<Urt>,
) {
    rcc_cr.modify(|r| r.set_hseon()); // HSE clock enable
    while !rcc_cr.load().hserdy() {} // HSE clock ready flag

    rcc_pllcfgr.store(|r| {
        r
            // HSE oscillator clock selected as PLL and PLLI2S clock entry
            .set_pllsrc()
            // division factor for PLL and PLLI2S input clock
            .write_pllm(PLL_M)
            // PLL multiplication factor for VCO
            .write_plln(PLL_N)
            // PLL division factor for main system clock
            .write_pllp(PLL_P / 2 - 1)
    });
    rcc_cr.modify(|r| r.set_pllon()); // PLL enable
    while !rcc_cr.load().pllrdy() {} // PLL clock ready flag

    flash_acr.store(|r| {
        r
            // the ratio of the CPU clock period to the Flash memory access time
            .write_latency(FLASH_WS)
            // data cache is enabled
            .set_dcen()
            // instruction cache is enabled
            .set_icen()
            // prefetch is enabled
            .set_prften()
    });
    while flash_acr.load().latency() != FLASH_WS {}

    rcc_cfgr.store(|r| {
        r
            // PLL selected as system clock
            .write_sw(0b10)
            // system clock not divided
            .write_hpre(0b0000)
            // APB1 = AHB / 2
            .write_ppre1(0b100)
            // APB2 = AHB / 1
            .write_ppre2(0b000)
    });
    while rcc_cfgr.load().sws() != 0b10 {} // PLL used as the system clock
}

use crate::thr;
use drone_cortexm::{fib, reg::prelude::*, thr::prelude::*};
use drone_stm32_map::reg;

async fn enable_hse_clock(
    rcc_cir: reg::rcc::Cir<Srt>,
    rcc_cr: reg::rcc::Cr<Srt>,
    thr_rcc: thr::Rcc,
) {
    // We need to move ownership of `hserdyc` and `hserdyf` into the following
    // fiber.
    let reg::rcc::Cir { hserdyc, hserdyf, .. } = rcc_cir;
    // Attach a listener that will notify us when RCC_CIR_HSERDYF is asserted.
    let hserdy = thr_rcc.add_future(fib::new_fn(move || {
        if hserdyf.read_bit() {
            hserdyc.set_bit();
            fib::Complete(())
        } else {
            fib::Yielded(())
        }
    }));
    // Enable the HSE clock.
    rcc_cr.modify(|r| r.set_hseon());
    // Sleep until RCC_CIR_HSERDYF is asserted.
    hserdy.await;
}

use drone_cortexm::reg::prelude::*;
use drone_stm32_map::periph::gpio::{
    periph_gpio_a3, periph_gpio_b14,
    pin::{GpioPinMap, GpioPinPeriph},
};

/// TPS22917 Load Switch.
pub struct LoadSwitch<T: GpioPinMap> {
    pin: GpioPinPeriph<T>,
}

impl<T: GpioPinMap> LoadSwitch<T> {
    /// Sets up a new [`LoadSwitch`].
    pub fn init(pin: GpioPinPeriph<T>) -> Self {
        pin.gpio_moder_moder.write_bits(0b01); // general purpose output
        Self { pin }
    }

    /// Turns the switch on.
    pub fn on(&self) {
        self.pin.gpio_bsrr_bs.set_bit(); // tie the pin to +3.3v
    }

    /// Turns the switch off.
    pub fn off(&self) {
        self.pin.gpio_bsrr_br.set_bit(); // tie the pin to ground
    }
}

pub fn handler(reg: Regs) {
    let sd_card_switch = LoadSwitch::init(periph_gpio_a3!(reg));
    let ble_switch = LoadSwitch::init(periph_gpio_b14!(reg));
    sd_card_switch.on();
    ble_switch.on();
}

use drone_core::log::Port;

fn handler() {
    // Familiar output macros just work!
    println!("Hello, world!");
    dbg!(123);

    // You can send raw bytes to different ports.
    Port::new(2).write_bytes(&[1, 2, 3]);

    // If a port accessed concurrently, you can send indivisible packets up to 4
    // bytes length.
    Port::new(3).write::<u32>(0xABFF_FFCD).write::<u32>(0xDCFF_FFBA);
}

/// The entry point.
///
/// # Safety
///
/// This function should only be called by hardware.
#[no_mangle]
pub unsafe extern "C" fn reset() -> ! {
    // Fill the memory region allocated for initially zeroed mutable static
    // variables with zeros. This is safe because none of these variables have
    // been in use before this line.
    unsafe { mem::bss_init() };
    // Fill the memory region for other mutable static variables with initial
    // values from flash memory. This is safe because none of these variables
    // have been in use before this line.
    unsafe { mem::data_init() };
    // Initialize the Floating Point Unit. This is safe because the unit has not
    // been in use before this line.
    unsafe { processor::fpu_init(true) };
    // Run the root task.
    tasks::root(
        // Instantiate a zero-sized collection of tokens for memory-mapped
        // registers. Safe only if this is the only instance.
        unsafe { Regs::take() },
        // Instantiate a zero-sized token needed to initialize the threading
        // system later. Safe only if this is the only instance.
        unsafe { ThrsInit::take() },
    );
    // If the root task returned, always sleep between interrupts.
    loop {
        processor::wait_for_int();
    }
}